1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and particularly, to a semiconductor memory device for storing data.
2. Description of the Related Art
In general, a semiconductor memory device is classified into a volatile memory device such as a dynamic random access memory (DRAM) or a static random access memory (SRAM) and a nonvolatile memory device such as a programmable read only memory (PROM), an erasable PROM (EPROM), or an electrically EPROM (EEPROM). The volatile memory device is distinguished from the nonvolatile memory device depending on whether data stored in a memory cell is retained after a certain time passes. In other words, in the volatile memory device, the data stored in the memory cell is not retained after the certain time passes. However, in the nonvolatile memory device, the data stored in the memory cell is retained after the certain time passes. Thus, in the case of the volatile memory device, a refresh operation is to be performed in order to retain data. However, the nonvolatile memory device may retain data without performing the refresh operation. Since the advantages of the nonvolatile memory device are suitable for low power consumption and high integration, the nonvolatile memory device has been extensively used as a storage medium of a portable device.
Meanwhile, with the development of the process technology of the semiconductor memory device, the degree of integration of the semiconductor memory device has been significantly increased. With the increase in the degree of integration, the chip size of the semiconductor memory device has been significantly reduced, and a distance between memory cells provided in the semiconductor memory device has also been significantly decreased. As a result, the distance has been decreased to such an extent that data stored in adjacent memory cells may have influence on each other. In this regard, in order to minimize interference between the adjacent memory cells, technology for randomizing and storing data has been developed. For such a data randomizing operation, an integrated circuit such as a linear feedback shift register and a seed value generator is generally used.
FIG. 1 is a block diagram illustrating a partial configuration of a conventional semiconductor memory device.
Referring to FIG. 1, the semiconductor memory device includes a random address generation unit 110, a signal mixing unit 120, a data input unit 130, a page buffering unit 140, and a memory cell array 150.
The random address generation unit 110 is for generating a random address RA and includes an initial value generation section 111 and a linear feedback shift register 112. The random address RA output from the linear feedback shift register 112 is to be matched with a column address due to the basic structure of the linear feedback shift register 112. Thus, the semiconductor memory device includes the initial value generation section 111 in order to ensure such a matching operation. The linear feedback shift register 112 generates the random address RA based on a seed value INT_SEED provided from the initial value generation section 111, and the generated random address RA is an address matched with the column address.
The signal mixing unit 120 mixes data DAT input through the data input unit 130 with the random address RA and outputs a mixing result to the page buffering unit 140. The data input unit 130 is a circuit for receiving the data DAT provided from the outside, and the page buffering unit 140 is a circuit for performing read and write operations and storing data in the memory cell array 150 or outputting the stored data.
The capacity of a semiconductor memory device has been increased more and more, resulting in an increase in the number of address bits. The increase in the number of address bits represents that the number of bits of the random address RA generated by the random address generation unit 110 is also to be increased. This causes an increase in the area of the initial value generation section 111 and the linear feedback shift register 112. The initial value generation section 111 and the linear feedback shift register 112 are complicated in terms of circuit design and occupy a relatively large area. An increase in the area of the initial value generation section 111 and the linear feedback shift register 112 may cause a burden in circuit layout design.